1. Field of the Invention
This invention relates generally to flip-flops having a synchronous reset and, more particularly, to a flip-flop having synchronous reset circuitry connected directly to the master section of the flip-flop, thereby bypassing load, enable and data gate circuitry.
2. Background Art
One type of previously known flip-flops comprise a data gate having a data input for generating internal data signals, a master section for receiving a clock signal and responsive to the internal data signals and for generating first and second signals indicative of the data input, and a slave section responsive to the first and second signals for storage therein and for generating traditional Q and Q outputs.
The data gate of this previously known flip-flop comprises a first transistor having a collector coupled to the master section and a base coupled to a first reference voltage by a first resistor and to the anode of a buffer diode. The cathode of the buffer diode is coupled to the data input. A second transistor has a collector connected to the master section and a base connected to the first reference voltage by a second resistor and to the anode of a diode. The cathode of this diode is coupled to the collector of the first transistor. The emitter of both the first and second transistors are connected together and coupled to the anode of one or more level setting diodes coupled in series. The cathode of the last diode in series is coupled to a second reference voltage. A synchronous reset signal is applied through a buffer circuit or load or enable gate circuit to the cathode of a Schottky diode. The anode of the Schottky diode is connected to the base of the first transistor. When the reset signal transitions low, the first transistor is biased off and the second transistor is biased on, causing the internal data signal to go low, regardless of the data input. Output Q would assume the low voltage level on the next triggering clock pulse.
However, this previously known circuitry has a relatively large set up and recovery time since the reset signal must pass through the load, enable, and data gate circuitry. Setup time is the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from low to high in order to be recognized and transferred to the outputs. Recovery time is the minimum time required between the end of the reset pulse and the clock transition from low to high in order to recognize and transfer high data to the Q outputs. Furthermore, the previously known circuitry has a larger input load and requires a higher current for the reset signal since it is routed through the load and enable gate circuits.
Therefore, what is needed is a flip-flop having an improved synchronous reset that reduces setup and recovery time, reduces supply current, simplifies layout by reducing component count, and reduces input load.